`timescale 1ns / 100ps

module right_rotate_tb();

    reg  [31:0] in_data;
    reg  [4:0]  dis;
    wire [31:0] out_data;

    initial begin
        $dumpfile("./output/right_rotate.vcd");
        $dumpvars(0, u_right_rotate);

        in_data = 32'b1;
        dis = 12;

        #10;
        dis = 1;

        #10;
        in_data = 32'hfffffff0;

        #10;
        dis = 19;

        #10;

        $finish;
    end

    right_rotate u_right_rotate(
        .in_data(in_data),
        .dis(dis),
        .out_data(out_data)
    );

endmodule